TSMC’s 2nm Node Progresses Smoothly, Eyes 2025 Launch for N3X and N2 Processes

May 24, 2024 – According to a report by MoneyDJ, a Taiwanese financial news outlet, TSMC’s executives revealed during the 2024 Technology Forum held in Hsinchu that the company’s 2nm node, utilizing Nanosheet (GAA transistors), is progressing smoothly.

TSMC’s Co-Deputy COO, Zhang Xiaoqiang, stated that the development of the 2nm process is “very smooth.” Currently, the “conversion performance” of the nanosheets has reached 90% of the target, with a yield rate exceeding 80%.

TSMC anticipates that its N2 process will continue to be the most advanced technology in the foundry industry when it is launched in 2025.

Additionally, according to Anandtech, TSMC plans to achieve mass production of the N2 process in the second half of 2025. During the same period, the company will also introduce the N3X process, which is targeted at HPC applications within its 3nm family.

The N3X process boasts a higher maximum voltage of 1.2V. Compared to the N3P process, it offers a 7% reduction in power consumption at the same frequency, a 5% improvement in performance at the same area, and a 10% increase in density at the same frequency. Previous reports indicate that the node is expected to start receiving wafers this year.

In the second half of 2026, TSMC plans to mass-produce two variants of the 2nm family processes: N2P and A16.

The N2P process promises a 5-10% reduction in power consumption at the same frequency and density compared to the N2 process, and a 5-10% improvement in performance at the same density and power consumption.

For the A16 node, TSMC will officially introduce back-side power delivery technology. This process can increase the frequency by 8-10% at the same operating voltage, reduce power consumption by 15-20% at the same frequency, and potentially increase density by up to 10%.

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