September 7, 2026 – Huawei officially unveiled the Mate XT 2 Ultimate Design tri-fold smartphone today, featuring the latest Kirin 9050 Pro chipset. This marks the first high-performance chip to adopt the “Tao Law” (τ Law). Furthermore, it represents Huawei’s return to releasing a brand-new Kirin chip at a flagship launch event after a six-year hiatus since the Mate 40 global launch.
Data released at the event reveals that the Kirin 9050 Pro features the LinxiCore CPU, which supports hyper-threading technology. This results in a 24% boost in single-core peak performance and a 52% increase in multi-core concurrent performance. On the graphics front, the new Maleoon GPU doubles the number of computing units and cache. It supports hardware-level ray tracing with a capability of 50 million rays, delivering a massive 142% improvement in rendering performance.
The core breakthrough of the Kirin 9050 Pro lies in its “logical folding” architecture. While traditional chips utilize a single-layer planar design, the Kirin 9050 Pro employs wafer-to-wafer hybrid bonding technology. This divides digital, analog, and storage circuits into vertically stacked active layers, restructuring them into a dual-layer 3D architecture. Simply put, it is akin to upgrading from a single-story house to a duplex, with added vertical interconnects that shorten signal transmission paths and reduce latency.
The theoretical foundation of this approach is the “Tao Law,” proposed by HiSilicon. In May of this year, He Tingbo published the initial paper on the Tao Law at the IEEE ISCAS conference. The core proposition advocates replacing “geometric scaling” with “time scaling.” By utilizing innovative technologies like logical folding to continuously compress signal propagation delays, the chip can enhance transistor density without relying on more advanced manufacturing processes. The V2 paper, released in July, supplemented extensive engineering details and empirical data, advancing the Tao Law from a theoretical framework to a quantifiable, roadmap-driven technical system.
Addressing the primary concern regarding heat dissipation in 3D stacked chips, He Tingbo responded in an updated paper on September 5 with empirical data: despite a 55% increase in transistor density, the power consumption of the NPU and GPU actually decreased under the same performance conditions. The core of the Tao Law is that τ represents a time-scaling law. While the folded architecture can operate at lower voltages and temperatures, or boost frequencies for stronger performance, it does not inherently equate to low power consumption. The key lies in utilizing vertical interconnects to shorten signal paths and optimize the time constant.
However, the logical folding in the Kirin 9050 Pro remains in a conservative stage. The current hybrid bonding pitch is 1.5 micrometers, with folding selectively applied only to critical paths rather than the entire chip, and TSV vias shifted down by just one layer compared to the top metal. He Tingbo set a target in her paper to reduce the aspect ratio to below 3. The full potential of logical folding will only be unleashed when the hybrid bonding pitch approaches the dimensions of the top metal wiring.
Looking ahead, the Kirin 2026 and Kirin 2027 have already completed tape-out, while the 2028 and 2029 versions are in the pre-tape-out phase. All four generations will adopt the logical folding architecture. In terms of frequency roadmap, the clock speeds from Kirin 2026 to Kirin 2029 will progressively scale up to 3.1GHz, 3.39GHz, 3.71GHz, and 4GHz.
