May 17, 2024 – Taiwan Semiconductor Manufacturing Company (TSMC) recently held a technology symposium announcing that its 3nm process node is on track, with the N3P node set to enter mass production in the second half of 2024.
The N3P, which is based on the N3E process node, promises further improvements in energy efficiency and transistor density. TSMC has stated that the yield rate of the N3E node has been further enhanced, now on par with its mature 5nm process.、
According to reports, TSMC executives revealed that the N3P process has already completed quality verification, with its yield rate approaching that of N3E. As an optically shrunk process, N3P is compatible with N3E in terms of IP modules, design rules, EDA tools, and methodologies. This compatibility has facilitated a smooth transition, as indicated by TSMC.
The key advantage of N3P lies in its enhanced specifications. Compared to N3E, chip designers can expect a performance improvement of approximately 4% at the same power consumption or a power reduction of about 9% at a matched clock speed. For typical chip designs consisting of logic, SRAM, and analog components, the transistor density has also increased by 4%.
