August 18, 2023 – In a stride toward technological innovation, Samsung Electronics is on track to usher in the next generation of V-NAND flash memory, planning to commence production of its 9th iteration by the coming year. This forthcoming iteration will employ a dual-stacked architecture with an impressive layer count surpassing 300.
Reports from DigiTimes have unveiled that this strategic move places Samsung ahead of its competitor SK Hynix. While the latter has set its sights on mass-producing 321-layer NAND flash memory with a three-tier stacked design by the first half of 2025, Samsung had already introduced a dual-stacked architecture back in 2020, rolling out the 7th generation of V-NAND flash memory chips.
This dual-stacked architecture involves the intricate production of a 3D NAND stack on a 300mm wafer, subsequently constructing another stack upon the foundation of the first. The introduction of the upcoming 9th generation V-NAND, with its layer count exceeding 300, is poised to significantly enhance the storage density achievable on a single wafer. This advancement, in turn, promises to drive down the costs associated with solid-state drives, a boon for consumers seeking efficient and affordable storage solutions.
On a competitive note, SK Hynix’s three-tier stacked architecture revolves around the creation of three distinct sets of 3D NAND layers. While this approach aims to maximize output, it unavoidably translates to added manufacturing steps and heightened utilization of raw materials.
Further insights from the Seoul Economic Daily suggest that following the rollout of the 9th generation 3D NAND, Samsung might venture into a three-tier stacked design for its 10th generation, expected to reach a staggering 430 layers. Industry insiders cite that surpassing the 400-layer threshold for 3D NAND could lead to escalated material costs and wafer expenditures. However, such a move could also safeguard healthy production output.
